Location
https://www.kennesaw.edu/ccse/events/computing-showcase/sp25-cday-program.php
Document Type
Event
Start Date
15-4-2025 4:00 PM
Description
This research focused on the implementation of modern computing systems by designing and simulating a 16-bit RISC-based ISA computer. The computer is built on a Von Neumann memory architecture with 1024×16-bit word-addressable space and a 6-bit ISA with 36 implemented instructions. The central processing unit (CPU) includes a control unit (CU) that automatically drives the fetch-decode-execute (FDE) cycle, four addressable general-purpose registers (GPRs), and an Arithmetic Logic Unit (ALU) comprising 21 operations and producing four flags. We validated the system by executing Euclid's GCD algorithm, generating the binaries with a custom assembler written in Python.
Included in
UR-114 K86: 16-Bit Computer Design, Optimization, and Implementation
https://www.kennesaw.edu/ccse/events/computing-showcase/sp25-cday-program.php
This research focused on the implementation of modern computing systems by designing and simulating a 16-bit RISC-based ISA computer. The computer is built on a Von Neumann memory architecture with 1024×16-bit word-addressable space and a 6-bit ISA with 36 implemented instructions. The central processing unit (CPU) includes a control unit (CU) that automatically drives the fetch-decode-execute (FDE) cycle, four addressable general-purpose registers (GPRs), and an Arithmetic Logic Unit (ALU) comprising 21 operations and producing four flags. We validated the system by executing Euclid's GCD algorithm, generating the binaries with a custom assembler written in Python.
